Timer Modes of operation

Timer 0 Modes of operation

Timer 0 has four operating modes. Operating modes can be selected by configuring T0M0 and T0M1 bit of TMOD register as shown in table.

T0M1---T0M0 ---Mode---- Description
0 -------0-------- Mode 0-- 8 bits
0 -------1 --------Mode 1 ---16 bits
1 -------0-------- Mode 2--- 8 bits with auto-reload
1------- 1-------- Mode 3----Split into two 8 bit timer/counters.


Timer 0 will start under either of following two conditions:

(1) If GATE0=0, Then TR0=1
(2) If GATE0=1, Then TR0=1 and INT0 Pin=1

From above discussion it is obvious that if only software control to run the timer 0 is required than clear GATE0 bit. In this case only software instruction, SETB TR0 will start the timer 0. If software and hardware both control is required to run the timer then set GATE0 bit. In this case only SETB TR0 software instruction will not run the timer 0 but INT0 pin status also must be 1 by hardware to run the timer 0.

Starting the timer will increments TH0-TL0 register every machine cycle if C/T0=0. If C/T0=1, then high to low transition on pin T0 (P3.4) will increments timer register. Timer will starts to increment from initialize value. When timer attains maximum value, then in next count it rolls to all zero. When timer rolls over from all one to all zero, timer 0 flag bit, TF0 will set and timer 0 interrupt request is generated.

If C/T0=1, then timer 0 counts external events occurring on pin T0. So, this is known as a counter operation of timer. The external input is sampled every machine cycle. When the sample is high in one cycle and low in the next one, the counter is incremented. Since it takes 2 machine cycles to recognize a high to low transition, the maximum count rate is oscillator frequency/24. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be high or low at least one machine cycle.


MODE 0

Clearing TMOD register bits T0M1 and T0M0 will select this operating mode. Instruction MOV TMOD, #xxxxxx00b will do this selection.

Mode 0 configures Timer 0 as a 13-bit Timer/Counter. TL0 uses only bit 0 to bit 4 and bit 5 to bit 7 are ignored. TL0 register bit 0 to bit 4 serve as the 5 LSBs of the 13-bit timer. TH0 provides the 8 MSBs of the 13-bit timer. As shown in Figure, 8-bit TH0 and 5-bit TL0 are connected in cascade to form 13-bit operation.

TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0

Starting the timer will increments 13-bit TH0-TL0 register. Timer will starts to increment from initialize value. When timer attains maximum value 1111 1111 11111b (1FFFH), then in next count it rolls to all zero. TF0 will set and timer 0 interrupt request is generated.

This sequence can be explained more clearly as following:

TH0 TL0
0000 0000 00000 ; It’s a initial value of timer register. We can initialize in the range of 0000 0000 00000 to 1111 1111 11111 by MOV instruction.
0000 0000 00001 ; First increment
…………………
…………………
0000 0000 11111 ; TL0(5-bit) atains its high value
0000 0001 00000 ; TL0(5-bit) overflows and increments TH0 registers.
0000 0001 00001
…………………
…………………
1111 1111 11111 ; Higher Value
0000 0000 00000 ; Timer 0 is overflowed. TF0 sets and Interrupt request is generated.

0000 0000 00001 ; timer will continue to increment.

MODE 1

Clearing TMOD register bit T0M1 and setting T0M0 will select this operating mode.

Mode 1 configures Timer 0 as a 16-bit Timer/Counter. As shown in Figure, 8-bit TH0 and 8-bit TL0 are connected in cascade to form 16-bit operation.


Starting the timer will increment 16-bit TH0-TL0 register. Timer will starts to increment from initialize value. When timer attains maximum value 1111 1111 1111 1111b (FFFFH), then in next count it rolls to all zero. TF0 will set and timer 0 interrupt request is generated.

This sequence can be explained more clearly as following:

TH0 TL0
0000 0000 0000 0000 ; It’s a initial value of timer register. We can initialize in the range
of 0000 0000 00000 to 1111 1111 11111 by MOV instruction.
0000 0000 0000 0001 ; First increment
…………………
…………………
0000 0000 1111 1111 ; TL0 atains its high value
0000 0001 0000 0000 ; TL0 overflows and increments TH0 registers.
0000 0001 0000 0001
…………………
…………………
1111 1111 1111 1111 ; Higher Value
0000 0000 0000 0000 ; Timer 0 is overflowed. TF0 sets and Interrupt request is
generated.
0000 0000 0000 0001 ; timer will continue to increment

MODE 2

Setting TMOD register bit T0M1 and clearing bit T0M0 will select this operating mode.

Mode 2 configures Timer 0 as a 8-bit auto reload Timer/Counter. TH0 holds the 8-bit reset value. TL0 is used to form 8-bit timer operation.

Starting the timer will increment 8-bit TL0 register. Timer will starts to increment from initialize value. When TL0 attains maximum value 1111 1111b (FFH), then in next count it loaded with contents of TH0 register. TF0 will set and timer 0 interrupt request is generated.

This sequence can be explained more clearly as following:

TL0
0101 0101 ; It’s a initial value loaded from TH0( Suppose[TH0]=55h) register. We can
initialize in the range of 0000 0000 to 1111 1111b by MOV instruction.
0101 0110 ; First increment
…………
…………
1111 1111 ; Higher Value
0101 0101 ; Timer 0 is overflowed and loaded with TH0 contents. TF0 sets and
Interrupt request is generated.
0101 0110 ; timer will continue to increment

MODE 3

Setting TMOD register bits T0M1 and T0M0 will select this operating mode.

Mode 3 configures Timer 0 as two 8-bit separate Timers. Register TL0 and TH0 both works as a two independent timers.

TL0 uses the timer 0 control bits C/T0 in the TMOD register and TR0 and TF0 in the TCON register. TH0 uses the timer 1 control bits TR1 and TF1 in the TCON register. TH0 can not perform counter operation.

In this mode TH0 uses control bits of timer 1, TR1 and TF1. So, without TR1 bit, timer 1 can start in free running by forcing it in mode 0, 1 or 2 and stop by forcing it in mode 3. Without TF1, interrupt facility is not available but timer 1 can be used as a baud rate generator.


Timer 1 Modes of operation

Timer 1 have also four operating modes. Operating modes can be selected by configuring T1M0 and T1M1 bit of TMOD register as shown in table.


T0M1 T0M0 Mode Description 0 0 Mode 0 8 bits 0 1 Mode 1 16 bits 1 0 Mode 2 8 bits with auto-reload 1 1 Mode 3 Split into two 8 bit timer/counters.

T1M1---T1M0 ---Mode---- Description
0 -------0-------- Mode 0-- 8 bits
0 -------1 --------Mode 1 ---16 bits
1 -------0-------- Mode 2--- 8 bits with auto-reload
1------- 1-------- Mode 3----Timer 1 is halted, but holds its count


Mode 0, mode 1 and Mode 2

These modes are identical to timer 0 mode 0, mode 1 and mode 2 respectively. In timer 1, bits T1M0, T1M1 C/T1, GATE1, TR1, TF1 and pin INT1 is utilizing instead of timer 0 bits T0M0, T0M1 C/T0, GATE0, TR0, TF0 and pin INT0 respectively.

Mode 3

In mode 3, Timer 1 is halted, but holds its count whatsoever. Without using TR1 bit, we can stop timer 1 by forcing it in this mode.