Timer SFRs

Following six SFRs plays important role for timer functions. And that’s why they are known as timer SFRs.

(1) TL0
(2) TH0
(3) TL1
(4) TH1
(5) TCON
(6) TMOD

(1) TL0- Timer 0 LSB register

Address: 8Ah
Reset value: 00000000b
Operation: Read and Write
Addressability: Byte. It can be address as TL0 or 8Ah in byte addressing



Bit Format:

7--------6------5-------4-------3-------2 -------1-------0

TL0.7 --TL0.6--TL0.5--TL0.4--TL0.3--TL0.2--TL0.1--TL0.0


(2) TH0- Timer 0 MSB register

Address: 8Ch
Reset value: 00000000b
Operation: Read and Write
Addressability: Byte. It can be address as TH0 or 8Ch in byte addressing


Bit Format:
7--------6------5-------4-------3-------2 -------1-------0

TH0.7--TH0.6--TH0.5--TH0.4--TH0.3--TH0.2--TH0.1--TH0.0


(3) TL1- Timer 1 LSB register

Address: 8Bh
Reset value: 00000000b
Operation: Read and Write
Addressability: Byte. It can be address as TL1 or 8Bh in byte addressing

Bit Format:
7--------6------5-------4-------3-------2 -------1-------0
TL1.7 --TL1.6--TL1.5--TL1.4--TL1.3--TL1.2--TL1.1--TL1.0

(4) TH1- Timer 1 MSB register

Address: 8Dh
Reset value: 00000000b
Operation: Read and Write
Addressability: Byte. It can be address as TH1 or 8Dh in byte addressing

Bit Format:
7--------6------5-------4-------3-------2 -------1-------0

TH1.7 --TH1.6--TH1.5--TH1.4 --TH1.3 --TH1.2 --TH1.1--TH1.1

(5) TCON : Timer/Counter Register

Address: 88h
Reset value: 00000000b
Operation: Read and Write
Addressability: Byte and Bit. It can be address as TCON.0, TCON.1, …, TCON.7 or 88.0h, 88.1h, …, 88.7 or by name of each bit (e.g. IT0) in bit addressing and TCON or 88h in byte addressing.

Bit Format:
7--------6------5-------4-------3-------2 -------1-------0

TF1----TR1----TF0----TR0----IE1-----IT1----IE0-----IT0

IT0
Bit 0
Interrupt 0 Type Select.

This bit selects whether the INT0 pin will detect edge orlevel triggered interrupts.
0 = INT0 is level triggered.
1 = INT0 is edge triggered


IE0
Bit 1
Interrupt 0 Edge Detect.

This bit is set when an edge/level of the type defined
by IT0 is detected. If IT0=1, this bit will remain set until cleared in software or the start of the External Interrupt 0 service routine.If IT0=0, this bit will inversely reflect the state of the INT0 pin.

IT1
Bit 2
Interrupt 1 Type Select.

This bit selects whether the INT1 pin will detect edge or level triggered interrupts.
0 = INT1 is level triggered.
1 = INT1 is edge triggered.

IE1
Bit 3
Interrupt 1 Edge Detect.

This bit is set when an edge/level of the type defined
by IT1 is detected. If IT10=1, this bit will remain set until cleared in software or the start of the External Interrupt 1 service routine.If IT1=0, this bit will inversely reflect the state of the INT1 pin.

TR0
Bit 4
Timer 0 Run Control.

This bit enables/disables the operation of Timer 0.
0 = Timer 0 is halted.
1 = Timer 0 is enabled

TF0
Bit 5
Timer 0 Overflow Flag.

This bit indicates when Timer 0 overflows its maximum count as defined by the current mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine or by software.
0 = No Timer 0 overflow has been detected.
1 = Timer 0 has overflowed its maximum count.

TR1
Bit 6
Timer 1 Run Control.

This bit enables/disables the operation of Timer 1.
0 = Timer 1 is halted.
1 = Timer 1 is enabled.

TF1
Bit 7
Timer 1 Overflow Flag.

This bit indicates when Timer 1 overflows its maximum count as defined by the current mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer1 interrupt service routine.
0 = No Timer 1 overflow has been detected.
1 = Timer 1 has overflowed its maximum count.



(6) TMOD : Timer Mode Control Register

Address: 89h
Reset value: 00000000b
Operation: Read and Write
Addressability: Byte. It can be address as TMOD or 89h in byte addressing.

Bit Format:
7--------6------5-------4-------3-------2 -------1-------0
GATE--C/ T---T1M1---T1M0--GATE---C/ T---T0M1---T0M0

T0M0
Bit 0
Timer 0 Mode Select.

T0M1
Bit 1
Timer 0 Mode Select.

C/T0
Bit 2
Timer 0 Counter/Timer Select.
0 = Timer 0 is incremented by internal clocks.
1 = Timer 0 is incremented by pulses on T0 when TR0 (TCON.4) is 1

GATE0
Bit 3
Timer 0 Gate Control.
This bit enable/disables the ability of Timer 0 to
increment.
0 = Timer 0 will clock when TR0=1, regardless of the state of INT0
1 = Timer 0 will clock only when TR0=1 and INT01

T1M1
Bit 4
Timer 1 Mode Select.

T1M1
Bit 5
Timer 1 Mode Select.

Bit 6
Timer 1 Counter/Timer Select.
0 = Timer 1 is incremented by internal clocks.
1 = Timer 1 is incremented by pulses on T1 when TR1 (TCON.6) is 1

GATE1
Bit 7
Timer 1 Gate Control.
This bit enable/disables the ability of Timer 1 to increment.
0 = Timer 1 will clock when TR1=1, regardless of the state of INT1
1 = Timer 1 will clock only when TR1=1 and INT1=1